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For many consumer audio and video products, NAND flash memory is a better storage choice than a hard drive, especially in low-capacity applications (4 Gbytes or less). As the quest continues for lower power, lighter, more robust products, NAND is proving to be very attractive.
The NAND flash array is grouped into a series of 128-kbyte blocks, which are the smallest erasable entity in a NAND device. Erasing a block sets all bits to "1" (all bytes to FFh). Programming is necessary to change erased bits from a 1 to a 0. The smallest entity that can be programmed is a byte. Some NOR Flash memory can perform read-while-write operations (Fig. 1). Although NAND can't perform read and write simultaneously, it can accomplish this at a system level using a method called shadowing, which has been used on PCs for years by loading the BIOS from the slower ROM into the higher-speed RAM.
NAND efficiencies are due to the lack of metal contacts in the NAND string. NAND flash cell size is smaller than NOR, 4F2 verses 10F2, due to the fact that NOR cells require a separate metal contact for each cell.
NAND is similar to a hard-disk drive. It's sector-based (page-based) and suited for storing sequential data such as pictures, audio, or PC data. Although random access can be accomplished at the system level by shadowing the data to RAM, doing so requires additional RAM storage. Also, like a hard disk, NAND devices have bad blocks, and require error-correcting code (ECC) to maintain data integrity.
1. The figure shows a comparison of various flash cells.
Due to the decrease in die area resulting from the small cell size, NAND provides the larger capacities required for today's low-cost consumer market. NAND flash is used in almost all removable memory cards. NAND's multiplexed interface provides a similar pin-out for all recent devices and densities. This pin-out lets designers use small densities and migrate to larger densities without any hardware changes to the pcb.
NAND vs. NOR
NAND's advantages are fast write (program) and erase operations, while NOR's advantages are random access and byte write capability (Fig. 2). NOR's random access ability allows for execute in place (XiP) capability, which is often a requirement in embedded applications. The disadvantages for NAND are slow random access, while NOR is hampered by are slow write and erase performance. NAND is better suited for file applications. However, more processors include a direct NAND interface and can boot directly from NAND (without NOR).
2. The random access time for NOR flash is specified at 0.12 Μs, whereas NAND random access is significantly slower for the first byte. Once the initial access is made, however, the remaining 2111 bytes are shifted out of NAND at only 0.03 Μs/byte.
The real benefits for NAND are faster program and erase times, as NAND provides over 5 Mbytes/s of sustained write performance. The block erase times are an impressive 2 ms for NAND versus 750 ms for NOR. Clearly, NAND has several significant positive attributes. However, it's not well-suited for direct random access.
NOR flash requires around 41 I/O pins for a 16-bit device, while NAND devices requires only 24 pins for a comparable interface. This pin savings comes from NAND's multiplexed command, address, and data bus. A benefit of the multiplexed interface is that larger NAND devices can be supported using the same hardware design and pcb. Because the common TSOP-1 package has been used for many years, this feature lets customers migrate to higher-density NAND devices on the same pcb. Another advantage of NAND is evident in it's packaging options: NAND offers a monolithic 2-Gbit die or can support up to four stacked die, allowing an 8-Gbit device in the same TSOP-1 package. This enables one package and interface to support higher densities in the future.
NAND basic operation
The 2-Gbit NAND device is organized as 2048 blocks, with 64 pages per block (Fig. 3). Each page has 2112 bytes total, comprised of a 2048-byte data area and a 64-byte spare area. The spare area is typically used for ECC, wear-leveling information, and other software overhead functions, although it's physically no different from the rest of the page. NAND devices are offered with either an 8- or 16-bit interface. Host data is connected to the NAND memory through a bidirectional data bus, 8 or 16 bits wide. In 16-bit mode, commands and addresses use only the lower 8 bits. The upper 8 bits are only used during data-transfer cycles.
3. The 2-Gbyte NAND device is organized as 2048 blocks.
Erasing a block requires about 2 ms. Once the data is loaded in the register, programming a page requires about 300 µs. A page read requires approximately 25 µs, in which the page is accessed from the array and loaded into the 16,896-bit register. The register is then available for the user to clock out the data.
In addition to the I/O bus, the NAND interface is comprised of six major control signals:
- Chip enable (CE#): If CE is not asserted, the NAND device will remain in standby mode and not respond to any control signals.
- Write enable (WE#): WE# is responsible for clocking data, address, or commands into the NAND.
- Read enable (RE#): RE# will enable the output data buffers.
- Command latch enable (CLE): When CLE is high, commands are latched into the NAND command register on the rising edge of the WE# signal.
- Address latch enable (ALE): When ALE is high, addresses are latched into the NAND address register on the rising edge of the WE# signal.
- Ready/busy (R/B#): If the NAND device is busy, the R/B# signal will be asserted low. This signal is open drain and needs a pull-up resistor.
Data is shifted into or out of the NAND register 16 or 8 bits at a time. When doing a Program operation, the data to be programmed is clocked into the data register on the rising edge of the WE#. Special commands are used to randomly access or move data around within the register to make random access easier.
Data is output from the data register in a similar fashion using the RE# signal, which is responsible for outputting the current data and incrementing to the next location. The WE# and RE# clocks can run as fast as 30 ns. When RE# or CE# aren't asserted low, the output buffers will be tri-stated. This combination of CE# and RE# enables the output buffers, allowing NAND flash to share the data bus with other types of memory like NOR, SRAM, or DRAM. This feature is sometimes called "chip enable don't care." The primary purpose of this reference is to accommodate older NAND devices, which require CE# to be asserted for the entire cycle.
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