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The convergence of mobile phones and other consumer-driven devices such as PDAs, MP3 players, and digital still and video cameras is progressing rapidly as evidenced by recent introductions of phones like the Motorola ROKR and Palm Treo. Consequently, the demand for processing power is increasing exponentially in these high-performance, low-power devices, and it becomes inevitable for mobile handset manufacturers to start adopting a dual-processor architecture (Fig. 1).
In the case of a PDA or smart phone, the two processing elements are typically a baseband processor and an application processor. The two processors operate independently, performing specialized tasks in the phone's architecture. The baseband processor acts as an RF modem, while the application processor runs the operating system and handles other multimedia features. High-level OSs, like Linux, Symbian, and Windows CE/Mobile, usually require a powerful application processor that also manages the audio, video, and other wireless features such as Wi-Fi and Bluetooth.
In 2G and 2.5G handsets, the two processors are interconnected by a traditional serial interface, either UART or SPI. These serial standards provide a low-bandwidth solution, typically not exceeding 1 Mbit/s in throughput; just enough for low data-rate traffic.
With the proliferation of 3G/3.5G networks, the multimedia rich content boosts the inter-processor communication bandwidth requirement significantly. As a result, the use of conventional serial interfaces becomes insufficient in 3G/3.5G applications (real-time video, music, games, etc.).
A new system-interconnect solution has recently emerged in the mobile handset space: the low-power dual-port memory. These memory devices, specifically designed for the wireless handset market, maximize throughput and minimize power consumption. The dual-ports have standard memory interfaces that can be connected seamlessly to all popular baseband and application processors. Moreover, by interfacing to the standard processor memory interface, the use of precious GPIO pins can also be minimized.
1. A dual-processor architecture is needed to handle all the features in 3G/3.5G handsets.
In a data-flow example, voice and multimedia data is received on the antenna connected to the baseband processor and this data is then packetized and sent to the application processor. The application processor either stores the multimedia content in a file system or displays/plays it in real time. The interconnect bandwidth between the baseband and application processors can become a bottleneck in next generation 3G/3.5G wireless mobile handsets.
Bandwidth requirement
Even in high-end 2G and 2.5G wireless handset designs, dual-processor architectures are widely implemented. However, the data rate in these networks is usually in the range of hundreds of kilobits per second, as most of the traffic is voice, simple e-mails, and text messages. Therefore, the inter-processor communication (IPC) in the current generation of wireless handsets is usually handled by serial interfaces like SPI, UART, or USB which need to be available on both processors. For instance, the GPRS and EDGE (2.5G) networks have maximum data rates of 171.2 and 384 kbits/s, respectively. On the other hand, the data rate for 3G/3.5G wireless standards, such as CDMA2000 and WCDMA with High-Speed Downlink Packet Access (HSDPA), can require a 10-Mbit/s or higher throughput to support multimedia rich content (Fig. 2).
2. The data-rate requirements for various wireless standards are shown.
Neither UART and SPI throughput (around 1 Mbit/s) can satisfy the demanding bandwidth of 3G/3.5G wireless networks (see the table). An interesting fact about the full-speed USB interfaces available in today's mobile wireless processors is that they offer a theoretical bandwidth of 12 Mbits/s. One would think this could satisfy the 3G/3.5G throughput requirement; however, with protocol overhead, the effective bandwidth may be less than 2 Mbits/s. Moreover, as the USB host port must be active at all times, this translates into power consumption even when no real data is passed through the interconnect channel. Furthermore, USB's high power consumption impacts its use as an IPC mechanism. Thus, none of the existing serial interfaces can provide sufficient data rates for a 3G/3.5G wireless handset. Moreover, the limited number of available USB ports on the processors can prevent it from being used for IPC, as USB ports are required for PC and peripheral connections.
Since the conception of the 3G/3.5G wireless network standards, smartphone and PDA mobile handset designers have been struggling to find an efficient processor interconnect solution. Many of the new designs include a combination of the existing serial standards, thus creating multiple data lanes that pump data from one processor to the other. While this may seem like a feasible solution, the software needed to handle this type of data flow becomes complex and prone to integrity issues. As these handset designs are time critical and their time-to-market determines a big chunk of their success, system designers can't afford to lose time worrying about inter-processor communication. Another solution employs a CPLD to interconnect the two processors.
The problem with this approach is four-fold. First, the CPLDs must be programmed, which takes more development time and resources. This introduces unnecessary complexity to the system design. Second, CPLDs usually take up more board space than other approaches, as these devices aren't optimized for mobile applications. Third, CPLDs increase the overall bill of materials, as it's a complicated piece of silicon and its cost can increase with the addition of development boards and other miscellaneous costs. Lastly, CPLDs usually consume more power than more application-specific devices. Thus, using a CPLD for IPC is far from a simple approach and it can potentially be detrimental to a mobile handset design.
Low-power dual-port for IPC
Low-power dual-port memory as a system interconnect implementation has recently emerged in the mobile handset space. Dual-port memories provide high-bandwidth throughput that can meet the needs of next-generation wireless data rates. While providing high effective bandwidth, dual-port memories maximize battery life by minimizing power consumption compared to serial interfaces.
Interfacing across a dual-port memory is also a straightforward process and employs mechanisms that designers are already familiar with. Memory interfaces are standard interfaces that connect seamlessly to off-the-shelf processors. In addition, no complex device drivers are required, as the "interface" is memory mapped between the processors, further simplifying software development and shortening product time to market.
Hardware interrupts provide a simple mechanism for processor handshaking, offering substantial efficiency and minimal protocol overhead for managing the communications link when compared to interfaces such as USB. This reduced overhead also conserves power by not requiring the processors on either side of the link to maintain a heavy/thick and cycle-hungry protocol stack that introduces unnecessary store and load operations.
The overall efficiency of low-power, dual-port IPCs has been further evaluated, as the effective rather than theoretical throughput is always the concern of handset designers when evaluating IPCs. To measure the effective throughput, Cypress and Texas Instruments (TI) have developed a platform comprising two TI OMAP1710 application processors with the Cypress CYDM256B16 low-power MoBL dual-port.
The software was developed on a Symbian 8.1 EKA1 OS platform, and a simple non-double/rotational buffered hardware interrupt scheme is used for handshaking. The throughput is calculated based on bursting data from the server to the client processor, with a preset packet size. Different packet sizes were used to benchmark the system's effective throughput, which varies with hardware interrupt frequency. The throughput performance can potentially improve with double/rotational buffer implementation (see the table). However, a more conservative approach was taken to simply software and minimize the number of interrupts generated (Fig. 3).
3. An effective throughput with different packet sizes is charted.
For example, consider a full-speed USB interconnect compared to a dual-port interface transferring a 1-Mbit multimedia file from the baseband processor to the application processor. A USB interface with a 2-Mbit/s effective throughput will take 0.5 s for the file to be completely transferred. This also has the effect that both serial interfaces on both processors must be awake for the duration of this data transfer with the relevant power consumption.
On the other hand, a low-power dual-port implemented as the processor interconnect will require only 0.02 s for the 1-Mbit file to be transferred at 48 Mbits/s. Moreover, the dual-port and the other processor can automatically enter a sleep mode after the data has been transferred. This reduces the time that both processors are burning power by over 96%.
The dual-port interconnect comes in a compact vfBGA package. Other features of low-power dual-ports, such as the input read and output drive registers, can also offload GPIO use on the processors (Fig. 4).
4. Shown are the uses of the input read register and output drive register.
About the authors
Danny Tseng is a senior applications engineer in the data communications division at Cypress Semiconductor. He received a Bachelor of Applied Science in Honors Electrical Engineering with Management Science option from the University of Waterloo in 2003. Tseng can be reached at ydt@cypress.com.
Lawrence Wong is a member of the group technical staff on TI's wireless application team. He received an MSEE degree and a BSEE from the University of Southern California. He can be reached at lawrence-wong@ti.com
lawrence-wong@ti.com.
Hung Vuong is a senior system architect and systems and software CTO for TI's Cellular Systems, Wireless Terminals Business Unit. He received BSEE from the University of Central Florida. Vuong can be reached at hqvuong@ti.com.
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