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Optimize inter-processor communication in dual baseband dual mode handsets

The onset of HSPA capable handsets, combined with improved video and data content quality, brews a perfect storm for many inter-processor communication architectures. Traditional interconnects can no longer support data throughputs in line with baseband processor capabilities and future mobile communication standards. Here's why multi-port interconnects may be a viable solution.

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Mobile Handset DesignLine

With the onset of globalization, world travel today is prevalent be it for business or leisure; and with travel comes the process of planning to carry the basic essentials and gadgets for the trip. Today's mobile handsets, thankfully, make it redundant to carry such other gadgets as MP3 players, portable navigation devices, cameras and handheld video games. With more than 1 billion units shipped annually, a mobile handset is now one of the basic necessities that people cannot leave home without. However, the phone is not of much use when it does not work in the destination country.

For example, Japan and Korea support a different standard (CDMA and FOMA) than most of Europe, which only supports GSM. Many other countries support both standards (GSM and CDMA) and it depends on the carrier subscribed to. A single handset, therefore, cannot be used worldwide. Many travelers carry two phones or buy a new Subscriber Identification Module (SIM) card at the airport whenever they are on travel, emailing the new number to their friends and colleagues.

This disconnect has given rise to Dual Baseband Dual Mode (DBDM) handsets that promise true operability worldwide as handset manufacturers compete to provide their users with the desired "global" roaming ability. A DBDM handset is a single handset that has 2 separate baseband processors. These handsets usually contain 2 slots for inserting a SIM card for use with GSM channels and Removable User Identification Module (RUIM) for use with CDMA channels. Phones that already have CDMA capabilities on board, however, might only provide one slot for inserting a GSM SIM card. Current major handset manufacturers that tout "World Phones" include Research In Motion (RIM), Samsung, LG, Motorola, and others.


Apart from processing their intended CDMA or GSM signals, each baseband processor is also given specific tasks to perform in the phone. These range from such simple applications as operating the keypad and LEDs to such complex functionalities as operating the LCD screen, camera, and video processing. With two separate processors receiving signals and various other applications split between them, data must be transferred between the processors in an efficient way to prevent delays for the end user, and have little or no impact on battery life. With the introduction of high resolution handset cameras and video streaming in handsets, we see larger file sizes and higher data rates that further amplify the need for efficient data handling between separate processors. How often have we been frustrated by our handsets "freezing" when accessing stored pictures or videos?

With telecommunication technology improving by leaps and bounds, no longer is air data transfer in the Kbps range as the 2.5/2.75G phones of yesteryears. Today's 3.5G HSPA capable phones require data transfer in the Mbps range. Future mobile communication standards that are currently in trials like WiMax, WiBro, LTE and UMB will further push the boundaries of data transfer. To match the increased speed dictated by these new standards, processors have increased in processing power and cellular networks have been upgraded to handle this exponential increase in data transfer.


Nevertheless, with the increase in processing power of baseband processors and the increase data capabilities of cellular networks, there remains an antiquated architecture within the handset that is limiting the handset's capability to perform at an optimum - the interprocessor communication architecture. This portion of the telecommunication ecosystem has been lagging behind compared to the exponential technological growth of the cellular handset industry. Currently, we have baseband and application processors that are capable of many Million Instructions per Second (MIPS) and data rates achieving 10Mbps or more for HSPA capable phones. However, with all the focus placed on processor capabilities and wireless data rates, the communication between processors has been a high profile bottleneck. This problem is faced by numerous handset designers that have the latest and greatest processors and chipsets to work with but cannot seem to increase the performance of their devices.

Current Solutions and their shortcomings


Current handset architectures today use various means of interprocessor communication. The popular direct interfaces currently in use include SPI, I2C, UART, and USB.

Although SPI is capable of data rates of above 20Mbps, there is no uniform specification for SPI and thus it is very dependent on the processor used. Typical SPI of baseband processors are approximately 16Mbps. With various baseband manufacturers producing their own proprietary products, the diverse SPI interfaces on separate baseband processors pose a daunting challenge for designers to pair two baseband processors successfully and achieve the optimum SPI speeds.

On the other hand, although the latest I2C specification calls for a high speed mode with throughputs up to 3.4Mbps, most devices available today are only capable of supporting data rates of between 400Kbps and 1Mbps. At these speeds, I2C is slow for telecommunication needs of today.

The third type of interconnect used in handsets is UART. UART typical data rate is approximately 1.5Mbps and a High Speed UART is capable of up to 5Mbps. However, such data rates are insufficient for high bandwidth interprocessor communication.

One of the more popular interconnect method is via USB (Universal Serial Bus). Most processors are equipped with Full Speed USB (FS-USB) device capability. FS-USB has a maximum data rate of 12Mbps that is in reality closer to 6Mbps throughput due to the high packet overhead necessary in the USB protocol. Furthermore, most baseband processors are not equipped with USB host capability which is necessary in a USB solution. Thus an additional USB host will have to be built in. Besides being inadequate for today's HSPA data rates, this also increases power consumption due to the USB host being constantly active even when no data is transmitted. The number of USB ports available on a baseband processor is also usually limited as it is the de-facto mode of connecting handsets to the PC.


Previously, for text messaging and simple data transfers on slower networks, interconnection methods mentioned might have been sufficient. With HSPA capable handsets attempting to reach 14.4Mbps and beyond, all of the current popular interfaces as seen above are unable to sustain the necessary throughput efficiently and at an optimum.

So how can designers address today's need for increase data throughput in handsets?

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