Review: Part I, Part II, and Part III.
Low Power Process and Transistor Technology
The genesis of low power electronics can be traced to the invention of the bipolar transistor in 1947. Elimination of the suppressive requirements for several watts of filament power and several hundred volts of anode voltage in vacuum tubes in exchange for transistor operation in the tens of milliwatts range was a breakthrough of unmatched importance in low power electronics. The capability to fully exploit the superb low power assets of the bipolar transistor was provided by a second breakthrough, the invention of the integrated circuit in 1958 (Figure 8).
Figure 8. First IC Made by Jack Kilby of Texas Instruments in 1958 (Source: www.ti.com)
Although far less widely acclaimed as such, a third breakthrough of indispensable importance to modern low power digital electronics was the CMOS integrated circuit announced in 1963. Collectively, these three inventions demonstrated the critical conceptual basis for modern low power electronics.
Process Technology Scaling
The semiconductor industry has been built on the benefits of traditional CMOS scaling. Classical scaling shrinks voltages along with the lithographic dimensions, and the results were that for a given die size, scaling delivered more gates, switching faster, at a constant power.
Scaling advanced CMOS technology to the next generation improves performance, increases transistor density, and reduces power consumption. Technology scaling typically has three main goals:
- Reduce gate delay by 30%, resulting in an increase in operating frequency of about 43%.
- Double transistor density.
- Reduce energy per transition by about 65%, saving 50% of power (at a 43% increase in frequency).
Unfortunately, some parameters have hard limits in scaling. A key component of the performance of CMOS transistors is the drive current or "Ion." This performance is proportional to the gate overdrive, or basically the supply voltage minus threshold voltage (Vt). If we continue scaling the supply voltage then the threshold voltage must also scale to keep up with the gate overdrives or to keep the gate overdrive up. CMOS transistors are not perfect switches. They have an off-state current that rises exponentially as the threshold voltage is reduced and so while lithographic dimensions continue to scale, voltage scaling itself has slowed down. The new realities of scaling are impacting both the static and dynamic power associated with products.
Scaling Theory
Scaling a technology reduces gate delay by 30% and the lateral and vertical dimensions by 30%. Therefore, the area and fringing capacitance, and consequently the total capacitance, decrease by 30% to 0.7.
Power Consumption
A chip's maximum power consumption depends on its technology as well as its implementation. According to scaling theory, a design ported to the next-generation technology should operate at 43% higher frequency.
If the supply voltage remains constant (constant voltage scaling), the power should remain the same. On the other hand, if the supply voltage scales down by 30% (constant electric field scaling), the power should decrease by 50%:
Unfortunately, logic designs ported to next-generation technologies with constant voltage scaling do not show a decrease in power; the power remains constant. On the other hand, logic designs ported to technologies using constant electric field scaling decrease in power. This is consistent with scaling theory.
However, the power dissipation of a chip depends not only on its technology, but also on its implementation, i.e. on size, circuit style, architecture, operation frequency, and so on.
Constant electric field scaling (supply voltage scaling) gives the lower energy delay product (ignoring leakage energy) and hence is preferable. However, it requires scaling threshold voltage (Vt) as well, which increases the sub-threshold leakage current, thus increasing the chip's leakage power.
Scaling Paradox
A consequence of scaling is rather undesirable, but until recently it has not been a particularly negative feature; the standby current density increases exponentially as the length scale is decreased. Figure 9 illustrates the passive power trend based on sub-threshold currents
Figure 9. Active (Dynamic) versus Static Leakage[2]
calculated from the industry trends of Vt, all for a junction temperature Tj = 25°C. For reference, the active power density is copied onto this scale to illustrate that the sub-threshold component of power dissipation is emerging to compete with the long-battled active power component for even the most power tolerant, high-speed CMOS applications.
As the lithography pushes forward, the product designer must devise new strategies to cope with the interference of passive power, which pushes for higher Vt (and thus higher VDD ) versus active power, which demands lower VDD and thus lower Vt . This results in fragmentation of device design points that address these conflicting needs in wafer fabrication.
The approach outlined in Table 2 allows the product designer flexibility to choose the best device match for active and passive power versus performance. Products that are very sensitive to passive power, such as portable and handheld devices, may sacrifice some performance to enable higher Vt . If these designs require higher performance, they are forced to sacrifice some switching power by use of correspondingly higher VDD as well.
Other applications may be challenged to inexpensively conduct heat generated by active power away from the integrated circuits and thus favor lower-VDD devices with low Vt and higher passive power. Thus, the variety of threshold voltages and power-supply voltages offered in 130nm technology has expanded to address these diverse needs.
Managing power as technology is scaled is a continual interaction between the product design needs and the physical constraints of the process technology. Figure 10 gives a good indication of those relationships.
Given a speed constraint, the goal is to find is the optimal supply voltage and the transistor threshold voltage while minimizing the power. Since these choices impact tradeoffs between static and dynamic power, then the application-dependent power constraints need to enter into that optimization level. Once a performance target has been set, a simple back-of-the-envelope analysis shows that the optimal supply voltage and the optimal threshold voltage choices imply a static power that is about 30% of the total power. The best choice depends on the average active power, which is strongly dependent on the circuit activity.
Figure 10. Threshold Voltage Tradeoff (Source www.freescale.com)
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