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Review: Part I, Part II, Part III.
and Part IV
Low Power Packaging Techniques
As mobile devices perform more in a smaller form factor, the technologies that enable them are challenged to do the same. As SoC vendors integrate more functionality into slimmer, smaller form factors, advanced packaging, along with SoC integration, is used to reduce the size, cost, and power consumption of the SoC ' s inside the mobile devices. New technologies, such as multi-die System-in-Package (SiP), stacked packages or Package-on-Package (PoP), packages integrating other packages or Package-in-Package (PiP), packages that integrate passives with silicon die, all promise to improve the power consumption, performance, and reduce package sizes. These innovations in SoC packaging technology enable vendors of converged products, such as cellular smartphones and portable media players, to create the small, thin, multi-function devices to meet their market demands.
The challenges of combining digital, analog and RF functions into a single piece of silicon and optimizing this for different process technologies has proved difficult and extremely costly. Although major advances are continuing to be made in the semiconductor industry, for highly complex systems containing multi-functional components (i.e. digital, analog, RF, MEMS, optics, etc.), the SoC option will be very costly if it can be achieved at all.
Dramatic increases in wireless communication and application processing, the number of radio interfaces, and the amount of memory integrated into advanced handsets are overwhelming compared to simple, voice-only designs. At the same time, handset users expect very small, sleek, low-cost handsets that feature large color displays and standby and talk times similar to those of voice-only handsets. In response, handset component manufacturers are moving aggressively to include advanced power-management techniques, specially tailoring communication and application processing architectures to the required tasks and dramatically reducing component cost.
The three main approaches to reduce component cost are SoC integration, SiP integration (the stacked-die solution), and PoP integration (the stacked package solution). System integration requires a complete system-level tradeoff analysis that involves the entire bill of materials and the architectures used for the communication system being designed.
Determining the best set of trade-offs to attain the most cost-effective solution requires close collaboration from diverse engineering disciplines, including process integration engineers, circuit engineers, and system engineers.
Figure 27 illustrates how SoC [17] for highly complex systems can become prohibitively expensive. It also details the different waves of packaging that have helped to produce decreases in system size and how this has coincided with Moore's law.
Innovative packaging technologies like SiP are viewed as a critical enabler in helping continue this trend and fill what is called the packaging gap.
Figure 27. (a) Packaging Waves (1970-2020) and (b) Costs of SiP versus SoC (Source: IZM Fraunhofer)
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