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With the wave of higher data rate and media-content available across the globe, media-intensive portable devices will be used continuously while relying on battery capacity similar to that of a voice-centric device. The portable devices that make use of these networks must be conscious of both power and performance. In particular, the processor design has to juggle many tradeoffs to strike the right balance. As process technology reduces into 90 and 65 nm nodes, performance and density are taken to new levels, yet power loss in both switching and leakage makes designing with these devices a major challenge. Power conversion efficiency today is already over 90%, and any improvement to the DC/DC converter itself would only provide minor impact to the overall system. Therefore, it has become necessary to use new techniques to manage energy at the system level. Some of these techniques will be explored in this article.
Dynamic and static power loss
The majority of processor power loss comes from dynamic switching loss and static leakage loss. The dynamic losses increase with operating frequency and number of gates. Static leakage loss increases as process geometry decreases. A simple equation can describe the combined dynamic and static power loss:
PLOSS = (αCVDD2f) + (VDDILEAK)
Where,
α = factor related to effective % of gates switching
C = circuit capacitance, a constant proportional to the number of gates and parasitic routing
f = clock frequency
The dynamic portion of the power loss equation (αCVDD2f) is due to the charging and discharging of the each transistor and its associated capacitance. The leakage portion of the power loss equation (VDDILEAK) is due primarily to gate and channel leakage in each transistor. Each of the power saving methods discussed below effect one or more of the variables in PLOSS equation. When to use which methods depends on many factors related the device and the application.
Leakage
Leakage power reduction is essential in sustaining the scaling of the CMOS process. Leakage power is now becoming proportional to dynamic or switching power loss in 90nm and below as shown in Figure 1. While lowering of the threshold voltage leads to significant increase in sub-threshold leakage current, the increase in gate tunneling leakage current is caused by thinner gate oxides. While scaling improves transistor density, functionality, and higher performance on chip, it also results in power dissipation increase. There are several methods such as high-k dielectrics, low power process, clock gating, and substrate biasing to combat and control leakage power. Several of these methods will be examined further to understand the pros and cons of each method.
Figure 1. Leakage vs. Dynamic power [1]
Low Power Process
One of the tools used to control leakage is semiconductor process optimizations. As transistors get smaller, gate oxide thickness is reduced. This affects the transistor in several ways. On the one hand, the threshold voltage and gate capacitance are decreased, allowing higher switching frequencies. On the other hand, the gate leakage increases (drain to source leakage, or sub-threshold leakage, also increases due to the channel length). Leakage at the 90 nm node and smaller can account for over half the power loss in a processor, so optimizations are made to the gate oxide thickness to make these processes viable. Typical offerings include a standard, low power, and high performance library. The low power libraries use a thicker gate oxide to drastically reduce gate leakage while only moderately reducing performance. Mixed libraries with a combination of standard, low power, and high performance offer a way to optimize different portions of a design for performance or power. While these libraries make it possible to trade performance with leakage, it is a fixed tradeoff that does not allow dynamic throttling of the leakage/performance.
Clock Gating
Logical operations happen with combinational logic gated at the input and output by flip-flops. Dynamic switching loss occurs in the combinational logic path when there is a change in the input. Some paths are exercised more than others, but on average, combinational logic only switches about 20--30% of the time. On the other hand, the flip-flops that gate each combinational logic operation are clocked 100% of the time, regardless of whether the input changed or not. Therefore, the dynamic switching loss of the flip-flops is significant even when there is no processing happening. The idea of clock gating is to mask the clock signal in the logic cells where there is no activity. By masking the clock signal, there is no switching loss in the flip-flops or the combination logic. This can be a very effective technique, but comes at the price of design complexity. As clock gating is used at lower levels of the design, the complexity generally goes up. Design automation tools are usually necessary to manage clock gating on large designs, and the effectiveness is generally influenced by the quality of the design software.
Substrate Biasing
Substrate biasing is a clever method to control the leakage/performance tradeoff using a voltage. Normally, Pwell and Nwell bulk substrates are connected to the source of their respective MOSFETs. The MOSFET is in saturation when VGS > VTH, and in cutoff when VGS < VTH. Ideally, there is no current flow from the drain to source when the MOSFET is in cutoff. However, as geometries become smaller and especially nodes 90 nm and below, substantial sub-threshold leakage current can flow. This is because miniaturization is achieved by reducing the channel resistance, which in turn reduces the threshold voltage of the devices. Since the sub-threshold leakage varies exponentially with the threshold voltage, it is only now becoming a major concern with < 90 nm technology.
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